HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
- x8 bus width.
- Address / Data Multiplexing
- Pinout compatiblity for all densities
- 3.3 V device : Vcc = 2.7 V ~3.6 V
MEMORY CELL ARRAY
- (2 K + 64) bytes x 64 pages x 1024 blocks
- (2 K + 64 spare) Bytes
- (128 K + 4 K spare) Bytes
PAGE READ / PROGRAM
- Random access : 25 us (max.)
- Sequential access : 25 ns (min.)
- Page program time : 200 us (typ.)
FAST BLOCK ERASE
- Block erase time: 2 ms (Typ)
- 1st cycle : Manufacturer Code
- 2nd cycle : Device Code
- 3rd cycle : Internal chip number, Cell Type, Number of
Simultaneously Programmed Pages.
- 4th cycle : Page size, Block size, Organization, Spare
COPY BACK PROGRAM
- Fast Data Copy without external buffering
- Internal buffer to improve the read throughput
CHIP ENABLE DON'T CARE
- Simple interface with microcontroller
- Normal Status Register (Read/Program/Erase)
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions.
- 100,000 Program/Erase cycles
(with 1 bit / 528 byte ECC)
- 10 years Data Retention
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- H27U1G8F2BTR-BX (Lead & Halogen Free)
: 63-Ball FBGA (9 x 11 x 1.0 mm)
- H27U1G8F2BFR-BX (Lead & Halogen Free)
Hynix NAND H27U1G8F2B Series have 128 M x 8 bit with spare 4 M x 8 bit capacity. The device is offered in 3.3 V Vcc
Power Supply, and with x8 I/O interface. Its NAND cell provides the most cost-effective solution for the solid state mass
storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data
while old data is erased.
The device contains 1024 blocks, composed by 64 pages. A program operation allows to write the 2112 byte page in
typical 200 us and an erase operation can be performed in typical 2.0 ms on a 128 K byte block.
Data in the page can be read out at 25ns cycle time per byte. The I/O pins serve as the ports for address and data input/
output as well as command input. This interface allows a reduced pin count and easy migration towards different densities,
without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, RE, ALE and CLE input pin. The on-chip
Program/Erase Controller automates all program and erase functions including pulse repetition, where required, and internal
verification and margining of data. The modify operations can be locked using the WP input.
The chip supports CE don't care function. This function allows the direct download of the code from the NAND Flash
memory device by a microcontroller, since the CE transitions do not stop the read operation.
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple
memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the H27U1G8F2B Series extended reliability of 100 K program/
erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial data
insertion phase. Data read out after copy back read is allowed.
This device includes also extra features like OTP/Unique ID area, Read ID2 extension.
The H27U1G8F2B is available in 48-TSOP1 12 x 20 mm and 63-FBGA 9 x 11 mm.