MC9S08AC128 8-Bit Microcontroller
8-Bit HCS08 Central Processor Unit (CPU)
• 40-MHz HCS08 CPU (central processor unit)
• 20-MHz internal bus frequency
• HC08 instruction set with added BGND, CALL and RTC instructions
• Memory Management Unit to support paged memory.
• Linear Address Pointer to allow direct page data accesses of the entire memory map
Development Support
• Background debugging system
• Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module)
• On-chip in-circuit emulator (ICE) Debug module containing three comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Supports both tag and force breakpoints.
Memory Options
• Up to 128K FLASH — read/program/erase over full operating voltage and temperature
• Up to 8K Random-access memory (RAM)
• Security circuitry to prevent unauthorized access to RAM and FLASH contents
Clock Source Options
• Clock source options include crystal, resonator, external clock, or internally generated clock with precision NVM trimming using ICG module
System Protection
• Optional computer operating properly (COP) reset with option to run from independent internal clock source or bus clock
• CRC module to support fast cyclic redundancy checks on system memory
• Low-voltage detection with reset or interrupt
• Illegal opcode detection with reset
• Master reset pin and power-on reset (POR)
Power-Saving Modes
• Wait plus two stops
Peripherals
• ADC — 16-channel, 10-bit resolution, 2.5 ms conversion time, automatic compare function, temperature sensor, internal bandgap reference channel
• SCIx — Two serial communications interface modules supporting LIN 2.0 Protocol and SAE J2602
protocols; Full duplex non-return to zero (NRZ); Master extended break generation; Slave extended break detection; Wakeup on active edge
• SPIx — One full and one master-only serial peripheral interface modules; Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting
• IIC — Inter-integrated circuit bus module; Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 10 bit addressing
• TPMx — One 2-channel and two 6-channel 16-bit timer/pulse-width modulator (TPM) modules: Selectable input capture, output compare, and edge-aligned PWM capability on each channel. Each timer module may be configured for buffered, centered PWM (CPWM) on all channels
• KBI — 8-pin keyboard interrupt module Input/Output
• Up to 70 general-purpose input/output pins
• Software selectable pullups on input port pins
• Software selectable drive strength and slew rate control on ports when used as outputs
Package Options
• 80-pin low-profile quad flat package (LQFP)
• 64-pin quad flat package (QFP)
• 48-pin quad flat no-lead package (QFN)
• 44-pin low-profile quad flat package (LQFP)
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