FEATURES
Voltage Supply: 2.6V ~ 3.6V
Organization
Memory Cell Array: (128M + 4M) x 8bit
Data Register: (2K + 64) x 8bit
Automatic Program and Erase
Page Program: (2K + 64) bytes
Block Erase: (128K + 4K) bytes
Page Read Operation
Page Size: (2K + 64) bytes
Random Read: 25us (Max.)
Serial Access: 25ns (Min.)
Memory Cell: 1bit/Memory Cell
Fast Write Cycle Time
Program time: 200us (Typ.)
Block Erase time: 1.5ms (Typ.)
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
Program/Erase Lockout During Power Transitions
Reliable CMOS Floating Gate Technology
Endurance:
100K Program/Erase Cycles (with 1 bit/528 bytes ECC)
Data Retention: 10 Years
Command Driven Operation
Cache Program Operation for High Performance Program
Copy-Back Operation
Unique ID for Copyright Protection
GENERAL DESCRIPTION
Offered in 128Mx8 bits, this device is 1Gbit with spare 32Mbit capacity. The device is offered in 3.3V VCC. Its NAND cell provides the most cost effective solution for the solid state mass storage market. A program operation can be performed in typical 200us on the 2,112-byte page and an erase operation can be performed in typical 1.5ms on a (128K+4K) bytes block. Data in the data register can be read out at 25ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of this device’s extended reliability of 100K program/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm. This device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
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